For connection in a multilayer wiring or between wiring layers in a semiconductor device, a method of manufacturing an embedded wiring structure using a metal material by removing an unnecessary wiring material by a CMP technique is used.
In a semiconductor device, in accordance with an increase in its integration degree, wirings and contact dimensions therebetween have been required to be miniaturized. In view of this, a favorable connection structure between wirings has been proposed (for example, see Patent Document 1) in order to prevent defective conduction between wirings that are miniaturized. In Patent Document 1, unevenness caused in a formation region of a wiring is planarized by gas ion irradiation, so that coverage by the wiring is improved.